A read path of a RAM (Random-access Memory) device may require a delay to be added to a clock path to strobe data in the center of an eye pattern. The delay of the clock relative to the arrival time of the data at the sampling point may be subject to process, voltage and temperature (PVT) variation, which may limit the speed of read operations. A method may be utilized for first removing process variation. Further updates may be applied to remove voltage variation and temperature variation.
Current solutions may utilize a Master delay cell to emulate a correct delay setting. The correct delay setting may then be applied to Slave delay cells within the actual clock path. The Master delay cell may then be monitored for voltage and temperature changes, corrected for said changes, and the Slave delay cells updated with the new setting. However, the current solutions may introduce mapping errors due to on-chip process variation from the Master to Slave delays. Further, the current solutions may require that data flow be interrupted in order to update the Slave delay cells. In addition, the currently implemented Master-to-Slave systems do not account for internal skew across multiple data paths which are strobed with a single clock. Still further, the currently implemented Master-to-Slave systems may have stringent duty cycle requirements. Also, current solutions may require custom-designed delay cells for reducing mapping error and may further require custom-designed overhead delay cells for accurately delaying data paths to match the clock path delay cell when the clock path delay cell is set to its minimum delay setting.
Another solution is described in co-pending and commonly owned patent application Ser. No. 11/523,139 (filed Sep. 19, 2006), which is incorporated by reference. Patent application Ser. No. 11/523,139 discloses a method which includes configuring an offline data path to match an online data path. The method further includes compensating the offline data path for voltage and temperature variation. The method further includes swapping the offline data path with the online data path. Further, swapping occurs automatically without interruption of data flow along the data paths. However, this method does not support passing of the strobed data directly to a standard FIFO (first-in first-out) buffer that is common in memory controllers. Instead, this solution is tied to the FIFO design described in paragraph [0017] of patent application Ser. No. 11/523,139. This FIFO design is specific to patent application Ser. No. 11/523,139 and wilt not always be desirable in all memory controller designs.
Therefore, it may be desirable to have a system and method for providing process, voltage and temperature compensation which addresses the above-referenced problems and limitations of the current solutions.